Semiconductor memory devices are generally classified as volatile memory devices and nonvolatile memory devices. Volatile memory devices lose stored data when power is turned off, but nonvolatile memory devices retain stored data even after power is turned off. Flash memory devices, like general nonvolatile memory devices, can be classified into a floating gate type and a charge trap type, depending on the kinds of data storage layers constituting a unit cell.
FIG. 1 is a partial schematic perspective view of a floating gate type flash memory device, illustrating a relationship between a floating gate voltage (Vfg) and parasitic capacitances (CFGA, CFGW). Referring to FIG. 1, a tunnel oxide layer 17, a floating gate 19, an inter-gate insulating layer 27 and a control gate 29 are sequentially formed over an active region 9 to thereby define a device isolation layer 13 formed on a semiconductor substrate 1. Here, the inter-gate insulating layer 27 may be formed as an oxide-nitride-oxide (ONO) layer. The active region 9 extends in a first direction (DA), which is a bitline direction, and the control gate 29 extends in a second direction (DW), which is a word line direction. An interlayer insulating layer 27 is interposed between the floating gates 19, as illustrated.
Reference symbols V and C illustrated in FIG. 1 show voltage and capacitance references. VFG denotes a voltage of the floating gate disposed in a central position (hereinafter, the central floating gate) among nine floating gates. VA denotes voltages of the floating gates adjacent in the first direction (DA) with respect to the central floating gate, and VW denotes voltage of the floating gate adjacent in the second direction (DW) with respect to the central floating gate. CFGA denotes a parasitic capacitance caused between the floating gates adjacent in the first direction (DA), and CFGW denotes a parasitic capacitance caused between the floating gates adjacent in the second direction (DW). As understood by those skilled in the art, the parasitic capacitances increase as the high integration of the memory devices is increased. As a distance between the active region 9 and an inter-gate insulating layer 27 is shortened, charges in the active region 9 may be trapped in the inter-gate insulating layer 27 and cause malfunction of a memory cell. Therefore, reliability and operational characteristics of the memory device may be degraded.